Mechanism to perform non-linear functions in a machine learning accelerator

ABSTRACT

An apparatus to facilitate execution of non-linear functions operations is disclosed. The apparatus comprises accelerator circuitry including a compute grid having a plurality of processing elements to execute neural network computations, store values resulting from the neural network computations, and perform piecewise linear (PWL) approximations of one or more non-linear functions using the stored values as input data.

FIELD

Embodiments relate generally to data processing and more particularly todata processing via a general-purpose graphics processing unit.

BACKGROUND OF THE DESCRIPTION

Deep learning algorithms are currently being implemented in variousmachine learning applications, such as audio/video recognition, videosummarization, etc. Neural networks of various forms (e.g.,Convolutional Neural Networks (CNNs), Recurrent Neural Networks (RNNs),Long Short-Term Memories (LSTMs), etc.) are applied to perform suchworkloads due to their highly parallel nature. Thus, Neural networks aresuitable for optimal implementations within single instruction multipledata (SIMD) architectures. Two dimensional (2-D) or higher dimensionalSIMD grids enable operand broadcast/sharing, which maximizes computesper byte fetched.

A basic component of any neural network is a three dimensional (3-D)convolution (or General Matrix Multiply (GEMM)) operation followed by anonlinear (NL) function (e.g., rectified linear unit (ReLU), tanh,sigmoid etc.). However, such NL functions are hardware intensive andcannot be easily mapped to 2-D SIMD grids.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentembodiments can be understood in detail, a more particular descriptionof the embodiments, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments and are therefore not to be considered limiting ofits scope.

FIG. 1 is a block diagram of a processing system, according to anembodiment.

FIG. 2 is a block diagram of an embodiment of a processor having one ormore processor cores, an integrated memory controller, and an integratedgraphics processor.

FIG. 3 is a block diagram of a graphics processor, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores.

FIG. 4 is a block diagram of a graphics processing engine of a graphicsprocessor in accordance with some embodiments.

FIG. 5 is a block diagram of hardware logic of a graphics processor coreaccording to some embodiments.

FIG. 6A-6B illustrate thread execution logic including an array ofprocessing elements employed in a graphics processor core according tosome embodiments.

FIG. 7 is a block diagram illustrating a graphics processor instructionformats according to some embodiments.

FIG. 8 is a block diagram of another embodiment of a graphics processor.

FIG. 9A is a block diagram illustrating a graphics processor commandformat according to an embodiment.

FIG. 9B is a block diagram illustrating a graphics processor commandsequence according to an embodiment.

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system according to some embodiments.

FIG. 11A is a block diagram illustrating an IP core development systemthat may be used to manufacture an integrated circuit to performoperations according to an embodiment.

FIG. 11B illustrates a cross-section side view of an integrated circuitpackage assembly according to some embodiments.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit that may be fabricated using one or more IP cores,according to an embodiment.

FIGS. 13A-13B are block diagrams illustrating exemplary graphicsprocessors for use within an System on Chip (SoC), according toembodiments described herein.

FIGS. 14A-14B illustrate additional exemplary graphics processor logicaccording to embodiments described herein.

FIG. 15 illustrates a machine learning software stack, according to anembodiment.

FIGS. 16A-16B illustrate layers of exemplary deep neural networks.

FIG. 17 illustrates an exemplary recurrent neural network.

FIG. 18 illustrates training and deployment of a deep neural network.

FIG. 19 is a block diagram illustrating distributed learning.

FIG. 20 illustrates a computing device employing a machine learningaccelerator, according to an embodiment.

FIG. 21 illustrates one embodiment of an accelerator.

FIG. 22 illustrates one embodiment of a processing element.

FIG. 23 is a graph of one embodiment of an approximation of a non-linearfunction.

FIG. 24 is a flow diagram illustrating one embodiment of a process forperforming neural network and non-linear functions at an accelerator.

FIG. 25 is flow diagram illustrating one embodiment of a process forperforming a non-linear computation at a processing element.

FIGS. 26A-26B illustrate a flow of a non-linear function computed at aprocessing element.

DETAILED DESCRIPTION

In embodiments, a hardware accelerator is implemented to compute machinelearning operations and non-linear functions. In such embodiments, apiecewise linear (PWL) approximation of the non-linear functions isperformed to compute the non-linear functions.

In the following description, numerous specific details are set forth toprovide a more thorough understanding. However, it will be apparent toone of skill in the art that the embodiments described herein may bepracticed without one or more of these specific details. In otherinstances, well-known features have not been described to avoidobscuring the details of the present embodiments.

System Overview

FIG. 1 is a block diagram of a processing system 100, according to anembodiment. In various embodiments, the system 100 includes one or moreprocessors 102 and one or more graphics processors 108, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 102 or processorcores 107. In one embodiment, the system 100 is a processing platformincorporated within a system-on-a-chip (SoC) integrated circuit for usein mobile, handheld, or embedded devices.

In one embodiment, the system 100 can include, or be incorporated withina server-based gaming platform, a game console, including a game andmedia console, a mobile gaming console, a handheld game console, or anonline game console. In some embodiments, the system 100 is a mobilephone, smart phone, tablet computing device or mobile Internet device.The processing system 100 can also include, couple with, or beintegrated within a wearable device, such as a smart watch wearabledevice, smart eyewear device, augmented reality device, or virtualreality device. In some embodiments, the processing system 100 is atelevision or set top box device having one or more processors 102 and agraphical interface generated by one or more graphics processors 108.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processor cores 107 is configured to process aspecific instruction set 109. In some embodiments, instruction set 109may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 107 may each process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 is additionally includedin processor 102 which may include different types of registers forstoring different types of data (e.g., integer registers, floating pointregisters, status registers, and an instruction pointer register). Someregisters may be general-purpose registers, while other registers may bespecific to the design of the processor 102.

In some embodiments, one or more processor(s) 102 are coupled with oneor more interface bus(es) 110 to transmit communication signals such asaddress, data, or control signals between processor 102 and othercomponents in the system 100. The interface bus 110, in one embodiment,can be a processor bus, such as a version of the Direct Media Interface(DMI) bus. However, processor busses are not limited to the DMI bus, andmay include one or more Peripheral Component Interconnect buses (e.g.,PCI, PCI Express), memory busses, or other types of interface busses. Inone embodiment the processor(s) 102 include an integrated memorycontroller 116 and a platform controller hub 130. The memory controller116 facilitates communication between a memory device and othercomponents of the system 100, while the platform controller hub (PCH)130 provides connections to I/O devices via a local I/O bus.

The memory device 120 can be a dynamic random access memory (DRAM)device, a static random access memory (SRAM) device, flash memorydevice, phase-change memory device, or some other memory device havingsuitable performance to serve as process memory. In one embodiment thememory device 120 can operate as system memory for the system 100, tostore data 122 and instructions 121 for use when the one or moreprocessors 102 executes an application or process. Memory controller 116also couples with an optional external graphics processor 112, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations. In some embodiments adisplay device 111 can connect to the processor(s) 102. The displaydevice 111 can be one or more of an internal display device, as in amobile electronic device or a laptop device or an external displaydevice attached via a display interface (e.g., DisplayPort, etc.). Inone embodiment the display device 111 can be a head mounted display(HMD) such as a stereoscopic display device for use in virtual reality(VR) applications or augmented reality (AR) applications.

In some embodiments the platform controller hub 130 enables peripheralsto connect to memory device 120 and processor 102 via a high-speed I/Obus. The I/O peripherals include, but are not limited to, an audiocontroller 146, a network controller 134, a firmware interface 128, awireless transceiver 126, touch sensors 125, a data storage device 124(e.g., hard disk drive, flash memory, etc.). The data storage device 124can connect via a storage interface (e.g., SATA) or via a peripheralbus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIExpress). The touch sensors 125 can include touch screen sensors,pressure sensors, or fingerprint sensors. The wireless transceiver 126can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile networktransceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver.The firmware interface 128 enables communication with system firmware,and can be, for example, a unified extensible firmware interface (UEFI).The network controller 134 can enable a network connection to a wirednetwork. In some embodiments, a high-performance network controller (notshown) couples with the interface bus 110. The audio controller 146, inone embodiment, is a multi-channel high definition audio controller. Inone embodiment the system 100 includes an optional legacy I/O controller140 for coupling legacy (e.g., Personal System 2 (PS/2)) devices to thesystem. The platform controller hub 130 can also connect to one or moreUniversal Serial Bus (USB) controllers 142 connect input devices, suchas keyboard and mouse 143 combinations, a camera 144, or other USB inputdevices.

It will be appreciated that the system 100 shown is exemplary and notlimiting, as other types of data processing systems that are differentlyconfigured may also be used. For example, an instance of the memorycontroller 116 and platform controller hub 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 112. In one embodiment the platform controller hub 130 and/ormemory controller 160 may be external to the one or more processor(s)102. For example, the system 100 can include an external memorycontroller 116 and platform controller hub 130, which may be configuredas a memory controller hub and peripheral controller hub within a systemchipset that is in communication with the processor(s) 102.

FIG. 2 is a block diagram of an embodiment of a processor 200 having oneor more processor cores 202A-202N, an integrated memory controller 214,and an integrated graphics processor 208. Those elements of FIG. 2having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor200 can include additional cores up to and including additional core202N represented by the dashed lined boxes. Each of processor cores202A-202N includes one or more internal cache units 204A-204N. In someembodiments each processor core also has access to one or more sharedcached units 206.

The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more PCI or PCI express busses. System agent core 210 providesmanagement functionality for the various processor components. In someembodiments, system agent core 210 includes one or more integratedmemory controllers 214 to manage access to various external memorydevices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, the systemagent core 210 also includes a display controller 211 to drive graphicsprocessor output to one or more coupled displays. In some embodiments,display controller 211 may also be a separate module coupled with thegraphics processor via at least one interconnect, or may be integratedwithin the graphics processor 208.

In some embodiments, a ring based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202A-202N and graphicsprocessor 208 use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-202Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment processor cores 202A-202N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. Additionally, processor200 can be implemented on one or more chips or as an SoC integratedcircuit having the illustrated components, in addition to othercomponents.

FIG. 3 is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 300 includes amemory interface 314 to access memory. Memory interface 314 can be aninterface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 320.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. The display device 320 can be an internal orexternal display device. In one embodiment the display device 320 is ahead mounted display device, such as a virtual reality (VR) displaydevice or an augmented reality (AR) display device. In some embodiments,graphics processor 300 includes a video codec engine 306 to encode,decode, or transcode media to, from, or between one or more mediaencoding formats, including, but not limited to Moving Picture ExpertsGroup (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formatssuch as H.264/MPEG-4 AVC, as well as the Society of Motion Picture &Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic ExpertsGroup (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, GPE 310 is a compute engine for performing graphicsoperations, including three-dimensional (3D) graphics operations andmedia operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the graphics processing engine (GPE) 410 is a version of theGPE 310 shown in FIG. 3. Elements of FIG. 4 having the same referencenumbers (or names) as the elements of any other figure herein canoperate or function in any manner similar to that described elsewhereherein, but are not limited to such. For example, the 3D pipeline 312and media pipeline 316 of FIG. 3 are illustrated. The media pipeline 316is optional in some embodiments of the GPE 410 and may not be explicitlyincluded within the GPE 410. For example and in at least one embodiment,a separate media and/or image processor is coupled to the GPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer403, which provides a command stream to the 3D pipeline 312 and/or mediapipelines 316. In some embodiments, command streamer 403 is coupled withmemory, which can be system memory, or one or more of internal cachememory and shared cache memory. In some embodiments, command streamer403 receives commands from the memory and sends the commands to 3Dpipeline 312 and/or media pipeline 316. The commands are directivesfetched from a ring buffer, which stores commands for the 3D pipeline312 and media pipeline 316. In one embodiment, the ring buffer canadditionally include batch command buffers storing batches of multiplecommands. The commands for the 3D pipeline 312 can also includereferences to data stored in memory, such as but not limited to vertexand geometry data for the 3D pipeline 312 and/or image data and memoryobjects for the media pipeline 316. The 3D pipeline 312 and mediapipeline 316 process the commands and data by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to a graphics core array 414. In one embodiment thegraphics core array 414 include one or more blocks of graphics cores(e.g., graphics core(s) 415A, graphics core(s) 415B), each blockincluding one or more graphics cores. Each graphics core includes a setof graphics execution resources that includes general-purpose andgraphics specific execution logic to perform graphics and computeoperations, as well as fixed function texture processing and/or machinelearning and artificial intelligence acceleration logic.

In various embodiments the 3D pipeline 312 includes fixed function andprogrammable logic to process one or more shader programs, such asvertex shaders, geometry shaders, pixel shaders, fragment shaders,compute shaders, or other shader programs, by processing theinstructions and dispatching execution threads to the graphics corearray 414. The graphics core array 414 provides a unified block ofexecution resources for use in processing these shader programs.Multi-purpose execution logic (e.g., execution units) within thegraphics core(s) 415A-414B of the graphic core array 414 includessupport for various 3D API shader languages and can execute multiplesimultaneous execution threads associated with multiple shaders.

In some embodiments the graphics core array 414 also includes executionlogic to perform media functions, such as video and/or image processing.In one embodiment, the execution units additionally includegeneral-purpose logic that is programmable to perform parallelgeneral-purpose computational operations, in addition to graphicsprocessing operations. The general-purpose logic can perform processingoperations in parallel or in conjunction with general-purpose logicwithin the processor core(s) 107 of FIG. 1 or core 202A-202N as in FIG.2.

Output data generated by threads executing on the graphics core array414 can output data to memory in a unified return buffer (URB) 418. TheURB 418 can store data for multiple threads. In some embodiments the URB418 may be used to send data between different threads executing on thegraphics core array 414. In some embodiments the URB 418 mayadditionally be used for synchronization between threads on the graphicscore array and fixed function logic within the shared function logic420.

In some embodiments, graphics core array 414 is scalable, such that thearray includes a variable number of graphics cores, each having avariable number of execution units based on the target power andperformance level of GPE 410. In one embodiment the execution resourcesare dynamically scalable, such that execution resources may be enabledor disabled as needed.

The graphics core array 414 couples with shared function logic 420 thatincludes multiple resources that are shared between the graphics coresin the graphics core array. The shared functions within the sharedfunction logic 420 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 414. In variousembodiments, shared function logic 420 includes but is not limited tosampler 421, math 422, and inter-thread communication (ITC) 423 logic.Additionally, some embodiments implement one or more cache(s) 425 withinthe shared function logic 420.

A shared function is implemented where the demand for a givenspecialized function is insufficient for inclusion within the graphicscore array 414. Instead a single instantiation of that specializedfunction is implemented as a stand-alone entity in the shared functionlogic 420 and shared among the execution resources within the graphicscore array 414. The precise set of functions that are shared between thegraphics core array 414 and included within the graphics core array 414varies across embodiments. In some embodiments, specific sharedfunctions within the shared function logic 420 that are used extensivelyby the graphics core array 414 may be included within shared functionlogic 416 within the graphics core array 414. In various embodiments,the shared function logic 416 within the graphics core array 414 caninclude some or all logic within the shared function logic 420. In oneembodiment, all logic elements within the shared function logic 420 maybe duplicated within the shared function logic 416 of the graphics corearray 414. In one embodiment the shared function logic 420 is excludedin favor of the shared function logic 416 within the graphics core array414.

FIG. 5 is a block diagram of hardware logic of a graphics processor core500, according to some embodiments described herein. Elements of FIG. 5having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Theillustrated graphics processor core 500, in some embodiments, isincluded within the graphics core array 414 of FIG. 4. The graphicsprocessor core 500, sometimes referred to as a core slice, can be one ormultiple graphics cores within a modular graphics processor. Thegraphics processor core 500 is exemplary of one graphics core slice, anda graphics processor as described herein may include multiple graphicscore slices based on target power and performance envelopes. Eachgraphics core 500 can include a fixed function block 530 coupled withmultiple sub-cores 501A-501F, also referred to as sub-slices, thatinclude modular blocks of general-purpose and fixed function logic.

In some embodiments the fixed function block 530 includes ageometry/fixed function pipeline 536 that can be shared by all sub-coresin the graphics processor 500, for example, in lower performance and/orlower power graphics processor implementations. In various embodiments,the geometry/fixed function pipeline 536 includes a 3D fixed functionpipeline (e.g., 3D pipeline 312 as in FIG. 3 and FIG. 4) a videofront-end unit, a thread spawner and thread dispatcher, and a unifiedreturn buffer manager, which manages unified return buffers, such as theunified return buffer 418 of FIG. 4.

In one embodiment the fixed function block 530 also includes a graphicsSoC interface 537, a graphics microcontroller 538, and a media pipeline539. The graphics SoC interface 537 provides an interface between thegraphics core 500 and other processor cores within a system on a chipintegrated circuit. The graphics microcontroller 538 is a programmablesub-processor that is configurable to manage various functions of thegraphics processor 500, including thread dispatch, scheduling, andpre-emption. The media pipeline 539 (e.g., media pipeline 316 of FIG. 3and FIG. 4) includes logic to facilitate the decoding, encoding,pre-processing, and/or post-processing of multimedia data, includingimage and video data. The media pipeline 539 implement media operationsvia requests to compute or sampling logic within the sub-cores 501-501F.

In one embodiment the SoC interface 537 enables the graphics core 500 tocommunicate with general-purpose application processor cores (e.g.,CPUs) and/or other components within an SoC, including memory hierarchyelements such as a shared last level cache memory, the system RAM,and/or embedded on-chip or on-package DRAM. The SoC interface 537 canalso enable communication with fixed function devices within the SoC,such as camera imaging pipelines, and enables the use of and/orimplements global memory atomics that may be shared between the graphicscore 500 and CPUs within the SoC. The SoC interface 537 can alsoimplement power management controls for the graphics core 500 and enablean interface between a clock domain of the graphic core 500 and otherclock domains within the SoC. In one embodiment the SoC interface 537enables receipt of command buffers from a command streamer and globalthread dispatcher that are configured to provide commands andinstructions to each of one or more graphics cores within a graphicsprocessor. The commands and instructions can be dispatched to the mediapipeline 539, when media operations are to be performed, or a geometryand fixed function pipeline (e.g., geometry and fixed function pipeline536, geometry and fixed function pipeline 514) when graphics processingoperations are to be performed.

The graphics microcontroller 538 can be configured to perform variousscheduling and management tasks for the graphics core 500. In oneembodiment the graphics microcontroller 538 can perform graphics and/orcompute workload scheduling on the various graphics parallel engineswithin execution unit (EU) arrays 502A-502F, 504A-504F within thesub-cores 501A-501F. In this scheduling model, host software executingon a CPU core of an SoC including the graphics core 500 can submitworkloads one of multiple graphic processor doorbells, which invokes ascheduling operation on the appropriate graphics engine. Schedulingoperations include determining which workload to run next, submitting aworkload to a command streamer, pre-empting existing workloads runningon an engine, monitoring progress of a workload, and notifying hostsoftware when a workload is complete. In one embodiment the graphicsmicrocontroller 538 can also facilitate low-power or idle states for thegraphics core 500, providing the graphics core 500 with the ability tosave and restore registers within the graphics core 500 across low-powerstate transitions independently from the operating system and/orgraphics driver software on the system.

The graphics core 500 may have greater than or fewer than theillustrated sub-cores 501A-501F, up to N modular sub-cores. For each setof N sub-cores, the graphics core 500 can also include shared functionlogic 510, shared and/or cache memory 512, a geometry/fixed functionpipeline 514, as well as additional fixed function logic 516 toaccelerate various graphics and compute processing operations. Theshared function logic 510 can include logic units associated with theshared function logic 420 of FIG. 4 (e.g., sampler, math, and/orinter-thread communication logic) that can be shared by each N sub-coreswithin the graphics core 500. The shared and/or cache memory 512 can bea last-level cache for the set of N sub-cores 501A-501F within thegraphics core 500, and can also serve as shared memory that isaccessible by multiple sub-cores. The geometry/fixed function pipeline514 can be included instead of the geometry/fixed function pipeline 536within the fixed function block 530 and can include the same or similarlogic units.

In one embodiment the graphics core 500 includes additional fixedfunction logic 516 that can include various fixed function accelerationlogic for use by the graphics core 500. In one embodiment the additionalfixed function logic 516 includes an additional geometry pipeline foruse in position only shading. In position-only shading, two geometrypipelines exist, the full geometry pipeline within the geometry/fixedfunction pipeline 516, 536, and a cull pipeline, which is an additionalgeometry pipeline which may be included within the additional fixedfunction logic 516. In one embodiment the cull pipeline is a trimmeddown version of the full geometry pipeline. The full pipeline and thecull pipeline can execute different instances of the same application,each instance having a separate context. Position only shading can hidelong cull runs of discarded triangles, enabling shading to be completedearlier in some instances. For example and in one embodiment the cullpipeline logic within the additional fixed function logic 516 canexecute position shaders in parallel with the main application andgenerally generates critical results faster than the full pipeline, asthe cull pipeline fetches and shades only the position attribute of thevertices, without performing rasterization and rendering of the pixelsto the frame buffer. The cull pipeline can use the generated criticalresults to compute visibility information for all the triangles withoutregard to whether those triangles are culled. The full pipeline (whichin this instance may be referred to as a replay pipeline) can consumethe visibility information to skip the culled triangles to shade onlythe visible triangles that are finally passed to the rasterizationphase.

In one embodiment the additional fixed function logic 516 can alsoinclude machine-learning acceleration logic, such as fixed functionmatrix multiplication logic, for implementations including optimizationsfor machine learning training or inferencing.

Within each graphics sub-core 501A-501F includes a set of executionresources that may be used to perform graphics, media, and computeoperations in response to requests by graphics pipeline, media pipeline,or shader programs. The graphics sub-cores 501A-501F include multiple EUarrays 502A-502F, 504A-504F, thread dispatch and inter-threadcommunication (TD/IC) logic 503A-503F, a 3D (e.g., texture) sampler505A-505F, a media sampler 506A-506F, a shader processor 507A-507F, andshared local memory (SLM) 508A-508F. The EU arrays 502A-502F, 504A-504Feach include multiple execution units, which are general-purposegraphics processing units capable of performing floating-point andinteger/fixed-point logic operations in service of a graphics, media, orcompute operation, including graphics, media, or compute shaderprograms. The TD/IC logic 503A-503F performs local thread dispatch andthread control operations for the execution units within a sub-core andfacilitate communication between threads executing on the executionunits of the sub-core. The 3D sampler 505A-505F can read texture orother 3D graphics related data into memory. The 3D sampler can readtexture data differently based on a configured sample state and thetexture format associated with a given texture. The media sampler506A-506F can perform similar read operations based on the type andformat associated with media data. In one embodiment, each graphicssub-core 501A-501F can alternately include a unified 3D and mediasampler. Threads executing on the execution units within each of thesub-cores 501A-501F can make use of shared local memory 508A-508F withineach sub-core, to enable threads executing within a thread group toexecute using a common pool of on-chip memory.

Execution Units

FIGS. 6A-6B illustrate thread execution logic 600 including an array ofprocessing elements employed in a graphics processor core according toembodiments described herein. Elements of FIGS. 6A-6B having the samereference numbers (or names) as the elements of any other figure hereincan operate or function in any manner similar to that describedelsewhere herein, but are not limited to such. FIG. 6A illustrates anoverview of thread execution logic 600, which can include a variant ofthe hardware logic illustrated with each sub-core 501A-501F of FIG. 5.FIG. 6B illustrates exemplary internal details of an execution unit.

As illustrated in FIG. 6A, in some embodiments thread execution logic600 includes a shader processor 602, a thread dispatcher 604,instruction cache 606, a scalable execution unit array including aplurality of execution units 608A-608N, a sampler 610, a data cache 612,and a data port 614. In one embodiment the scalable execution unit arraycan dynamically scale by enabling or disabling one or more executionunits (e.g., any of execution unit 608A, 608B, 608C, 608D, through608N-1 and 608N) based on the computational requirements of a workload.In one embodiment the included components are interconnected via aninterconnect fabric that links to each of the components. In someembodiments, thread execution logic 600 includes one or more connectionsto memory, such as system memory or cache memory, through one or more ofinstruction cache 606, data port 614, sampler 610, and execution units608A-608N. In some embodiments, each execution unit (e.g. 608A) is astand-alone programmable general-purpose computational unit that iscapable of executing multiple simultaneous hardware threads whileprocessing multiple data elements in parallel for each thread. Invarious embodiments, the array of execution units 608A-608N is scalableto include any number individual execution units.

In some embodiments, the execution units 608A-608N are primarily used toexecute shader programs. A shader processor 602 can process the variousshader programs and dispatch execution threads associated with theshader programs via a thread dispatcher 604. In one embodiment thethread dispatcher includes logic to arbitrate thread initiation requestsfrom the graphics and media pipelines and instantiate the requestedthreads on one or more execution unit in the execution units 608A-608N.For example, a geometry pipeline can dispatch vertex, tessellation, orgeometry shaders to the thread execution logic for processing. In someembodiments, thread dispatcher 604 can also process runtime threadspawning requests from the executing shader programs.

In some embodiments, the execution units 608A-608N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. The execution units support vertex and geometry processing(e.g., vertex programs, geometry programs, vertex shaders), pixelprocessing (e.g., pixel shaders, fragment shaders) and general-purposeprocessing (e.g., compute and media shaders). Each of the executionunits 608A-608N is capable of multi-issue single instruction multipledata (SIMD) execution and multi-threaded operation enables an efficientexecution environment in the face of higher latency memory accesses.Each hardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state.Execution is multi-issue per clock to pipelines capable of integer,single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and othermiscellaneous operations. While waiting for data from memory or one ofthe shared functions, dependency logic within the execution units608A-608N causes a waiting thread to sleep until the requested data hasbeen returned. While the waiting thread is sleeping, hardware resourcesmay be devoted to processing other threads. For example, during a delayassociated with a vertex shader operation, an execution unit can performoperations for a pixel shader, fragment shader, or another type ofshader program, including a different vertex shader.

Each execution unit in execution units 608A-608N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 608A-608N support integer andfloating-point data types.

The execution unit instruction set includes SIMD instructions. Thevarious data elements can be stored as a packed data type in a registerand the execution unit will process the various elements based on thedata size of the elements. For example, when operating on a 256-bit widevector, the 256 bits of the vector are stored in a register and theexecution unit operates on the vector as four separate 64-bit packeddata elements (Quad-Word (QW) size data elements), eight separate 32-bitpacked data elements (Double Word (DW) size data elements), sixteenseparate 16-bit packed data elements (Word (W) size data elements), orthirty-two separate 8-bit data elements (byte (B) size data elements).However, different vector widths and register sizes are possible.

In one embodiment one or more execution units can be combined into afused execution unit 609A-609N having thread control logic (607A-607N)that is common to the fused EUs. Multiple EUs can be fused into an EUgroup. Each EU in the fused EU group can be configured to execute aseparate SIMD hardware thread. The number of EUs in a fused EU group canvary according to embodiments. Additionally, various SIMD widths can beperformed per-EU, including but not limited to SIMD8, SIMD16, andSIMD32. Each fused graphics execution unit 609A-609N includes at leasttwo execution units. For example, fused execution unit 609A includes afirst EU 608A, second EU 608B, and thread control logic 607A that iscommon to the first EU 608A and the second EU 608B. The thread controllogic 607A controls threads executed on the fused graphics executionunit 609A, allowing each EU within the fused execution units 609A-609Nto execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 606) are included in thethread execution logic 600 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In someembodiments, a sampler 610 is included to provide texture sampling for3D operations and media sampling for media operations. In someembodiments, sampler 610 includes specialized texture or media samplingfunctionality to process texture or media data during the samplingprocess before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 600 via thread spawningand dispatch logic. Once a group of geometric objects has been processedand rasterized into pixel data, pixel processor logic (e.g., pixelshader logic, fragment shader logic, etc.) within the shader processor602 is invoked to further compute output information and cause resultsto be written to output surfaces (e.g., color buffers, depth buffers,stencil buffers, etc.). In some embodiments, a pixel shader or fragmentshader calculates the values of the various vertex attributes that areto be interpolated across the rasterized object. In some embodiments,pixel processor logic within the shader processor 602 then executes anapplication programming interface (API)-supplied pixel or fragmentshader program. To execute the shader program, the shader processor 602dispatches threads to an execution unit (e.g., 608A) via threaddispatcher 604. In some embodiments, shader processor 602 uses texturesampling logic in the sampler 610 to access texture data in texture mapsstored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 614 provides a memory accessmechanism for the thread execution logic 600 to output processed data tomemory for further processing on a graphics processor output pipeline.In some embodiments, the data port 614 includes or couples to one ormore cache memories (e.g., data cache 612) to cache data for memoryaccess via the data port.

As illustrated in FIG. 6B, a graphics execution unit 608 can include aninstruction fetch unit 637, a general register file array (GRF) 624, anarchitectural register file array (ARF) 626, a thread arbiter 622, asend unit 630, a branch unit 632, a set of SIMD floating point units(FPUs) 634, and in one embodiment a set of dedicated integer SIMD ALUs635. The GRF 624 and ARF 626 includes the set of general register filesand architecture register files associated with each simultaneoushardware thread that may be active in the graphics execution unit 608.In one embodiment, per thread architectural state is maintained in theARF 626, while data used during thread execution is stored in the GRF624. The execution state of each thread, including the instructionpointers for each thread, can be held in thread-specific registers inthe ARF 626.

In one embodiment the graphics execution unit 608 has an architecturethat is a combination of Simultaneous Multi-Threading (SMT) andfine-grained Interleaved Multi-Threading (IMT). The architecture has amodular configuration that can be fine-tuned at design time based on atarget number of simultaneous threads and number of registers perexecution unit, where execution unit resources are divided across logicused to execute multiple simultaneous threads.

In one embodiment, the graphics execution unit 608 can co-issue multipleinstructions, which may each be different instructions. The threadarbiter 622 of the graphics execution unit thread 608 can dispatch theinstructions to one of the send unit 630, branch unit 642, or SIMDFPU(s) 634 for execution. Each execution thread can access 128general-purpose registers within the GRF 624, where each register canstore 32 bytes, accessible as a SIMD 8-element vector of 32-bit dataelements. In one embodiment, each execution unit thread has access to 4Kbytes within the GRF 624, although embodiments are not so limited, andgreater or fewer register resources may be provided in otherembodiments. In one embodiment up to seven threads can executesimultaneously, although the number of threads per execution unit canalso vary according to embodiments. In an embodiment in which seventhreads may access 4 Kbytes, the GRF 624 can store a total of 28 Kbytes.Flexible addressing modes can permit registers to be addressed togetherto build effectively wider registers or to represent strided rectangularblock data structures.

In one embodiment, memory operations, sampler operations, and otherlonger-latency system communications are dispatched via “send”instructions that are executed by the message passing send unit 630. Inone embodiment, branch instructions are dispatched to a dedicated branchunit 632 to facilitate SIMD divergence and eventual convergence.

In one embodiment the graphics execution unit 608 includes one or moreSIMD floating point units (FPU(s)) 634 to perform floating-pointoperations. In one embodiment, the FPU(s) 634 also support integercomputation. In one embodiment the FPU(s) 634 can SIMD execute up to Mnumber of 32-bit floating-point (or integer) operations, or SIMD executeup to 2M 16-bit integer or 16-bit floating-point operations. In oneembodiment, at least one of the FPU(s) provides extended math capabilityto support high-throughput transcendental math functions and doubleprecision 64-bit floating-point. In some embodiments, a set of 8-bitinteger SIMD ALUs 635 are also present, and may be specificallyoptimized to perform operations associated with machine learningcomputations.

In one embodiment, arrays of multiple instances of the graphicsexecution unit 608 can be instantiated in a graphics sub-core grouping(e.g., a sub-slice). For scalability, product architects can choose theexact number of execution units per sub-core grouping. In one embodimentthe execution unit 608 can execute instructions across a plurality ofexecution channels. In a further embodiment, each thread executed on thegraphics execution unit 608 is executed on a different channel.

FIG. 7 is a block diagram illustrating a graphics processor instructionformats 700 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 700 described and illustrated are macro-instructions,in that they are instructions supplied to the execution unit, as opposedto micro-operations resulting from instruction decode once theinstruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit instruction format 710. A 64-bitcompacted instruction format 730 is available for some instructionsbased on the selected instruction, instruction options, and number ofoperands. The native 128-bit instruction format 710 provides access toall instruction options, while some options and operations arerestricted in the 64-bit format 730. The native instructions availablein the 64-bit format 730 vary by embodiment. In some embodiments, theinstruction is compacted in part using a set of index values in an indexfield 713. The execution unit hardware references a set of compactiontables based on the index values and uses the compaction table outputsto reconstruct a native instruction in the 128-bit instruction format710.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). Forinstructions in the 128-bit instruction format 710 an exec-size field716 limits the number of data channels that will be executed inparallel. In some embodiments, exec-size field 716 is not available foruse in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 720, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726 specifying, for example, whether directregister addressing mode or indirect register addressing mode is used.When direct register addressing mode is used, the register address ofone or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode isused to define a data access alignment for the instruction. Someembodiments support access modes including a 16-byte aligned access modeand a 1-byte aligned access mode, where the byte alignment of the accessmode determines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction may use 16-byte-aligned addressing for all sourceand destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction directly provide the register address of one or moreoperands. When indirect register addressing mode is used, the registeraddress of one or more operands may be computed based on an addressregister value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 8 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a geometry pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general-purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A-852B via a thread dispatcher831.

In some embodiments, execution units 852A-852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A-852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, geometry pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to geometry pipeline 820. Insome embodiments, if tessellation is not used, tessellation components(e.g., hull shader 811, tessellator 813, and domain shader 817) can bebypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A-852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 873 in the render output pipeline870 dispatches pixel shaders to convert the geometric objects into perpixel representations. In some embodiments, pixel shader logic isincluded in thread execution logic 850. In some embodiments, anapplication can bypass the rasterizer and depth test component 873 andaccess un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A-852B and associated logic units (e.g.,L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via adata port 856 to perform memory access and communicate with renderoutput pipeline components of the processor. In some embodiments,sampler 854, caches 851, 858 and execution units 852A-852B each haveseparate memory access paths. In one embodiment the texture cache 858can also be configured as a sampler cache.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front-end 834. In some embodiments, videofront-end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 837 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, the geometry pipeline 820 and media pipeline 830are configurable to perform operations based on multiple graphics andmedia programming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL), Open Computing Language (OpenCL),and/or Vulkan graphics and compute API, all from the Khronos Group. Insome embodiments, support may also be provided for the Direct3D libraryfrom the Microsoft Corporation. In some embodiments, a combination ofthese libraries may be supported. Support may also be provided for theOpen Source Computer Vision Library (OpenCV). A future API with acompatible 3D pipeline would also be supported if a mapping can be madefrom the pipeline of the future API to the pipeline of the graphicsprocessor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 9A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 900 of FIG. 9A includes data fields to identify a client902, a command operation code (opcode) 904, and data 906 for thecommand. A sub-opcode 905 and a command size 908 are also included insome commands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 904 and, if present, sub-opcode 905 to determine theoperation to perform. The client unit performs the command usinginformation in data field 906. For some commands an explicit commandsize 908 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word.

The flow diagram in FIG. 9B illustrates an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command 912 is required immediatelybefore a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 916 includes selecting the size and number of returnbuffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930 or the media pipeline 924 beginning at themedia pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D statesetting commands for vertex buffer state, vertex element state, constantcolor state, depth buffer state, and other state variables that are tobe configured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based on the particular3D API in use. In some embodiments, 3D pipeline state 930 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment, commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general-purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of commands to configure the mediapipeline state 940 are dispatched or placed into a command queue beforethe media object commands 942. In some embodiments, commands for themedia pipeline state 940 include data to configure the media pipelineelements that will be used to process the media objects. This includesdata to configure the video decode and video encode logic within themedia pipeline, such as encode or decode format. In some embodiments,commands for the media pipeline state 940 also support the use of one ormore pointers to “indirect” state elements that contain a batch of statesettings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system 1000 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application1010, an operating system 1020, and at least one processor 1030. In someembodiments, processor 1030 includes a graphics processor 1032 and oneor more general-purpose processor core(s) 1034. The graphics application1010 and operating system 1020 each execute in the system memory 1050 ofthe data processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 1014 in a machinelanguage suitable for execution by the general-purpose processor core1034. The application also includes graphics objects 1016 defined byvertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 1020 can support agraphics API 1022 such as the Direct3D API, the OpenGL API, or theVulkan API. When the Direct3D API is in use, the operating system 1020uses a front-end shader compiler 1024 to compile any shader instructions1012 in HLSL into a lower-level shader language. The compilation may bea just-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 1010. In some embodiments, the shader instructions 1012 areprovided in an intermediate form, such as a version of the StandardPortable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 11A is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh-level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 1112. The simulation model 1112 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design 1115 can then be created or synthesized from thesimulation model 1112. The RTL design 1115 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 1115, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3^(rd)party fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

FIG. 11B illustrates a cross-section side view of an integrated circuitpackage assembly 1170, according to some embodiments described herein.The integrated circuit package assembly 1170 illustrates animplementation of one or more processor or accelerator devices asdescribed herein. The package assembly 1170 includes multiple units ofhardware logic 1172, 1174 connected to a substrate 1180. The logic 1172,1174 may be implemented at least partly in configurable logic orfixed-functionality logic hardware, and can include one or more portionsof any of the processor core(s), graphics processor(s), or otheraccelerator devices described herein. Each unit of logic 1172, 1174 canbe implemented within a semiconductor die and coupled with the substrate1180 via an interconnect structure 1173. The interconnect structure 1173may be configured to route electrical signals between the logic 1172,1174 and the substrate 1180, and can include interconnects such as, butnot limited to bumps or pillars. In some embodiments, the interconnectstructure 1173 may be configured to route electrical signals such as,for example, input/output (I/O) signals and/or power or ground signalsassociated with the operation of the logic 1172, 1174. In someembodiments, the substrate 1180 is an epoxy-based laminate substrate.The package substrate 1180 may include other suitable types ofsubstrates in other embodiments. The package assembly 1170 can beconnected to other electrical devices via a package interconnect 1183.The package interconnect 1183 may be coupled to a surface of thesubstrate 1180 to route electrical signals to other electrical devices,such as a motherboard, other chipset, or multi-chip module.

In some embodiments, the units of logic 1172, 1174 are electricallycoupled with a bridge 1182 that is configured to route electricalsignals between the logic 1172, 1174. The bridge 1182 may be a denseinterconnect structure that provides a route for electrical signals. Thebridge 1182 may include a bridge substrate composed of glass or asuitable semiconductor material. Electrical routing features can beformed on the bridge substrate to provide a chip-to-chip connectionbetween the logic 1172, 1174.

Although two units of logic 1172, 1174 and a bridge 1182 areillustrated, embodiments described herein may include more or fewerlogic units on one or more dies. The one or more dies may be connectedby zero or more bridges, as the bridge 1182 may be excluded when thelogic is included on a single die. Alternatively, multiple dies or unitsof logic can be connected by one or more bridges. Additionally, multiplelogic units, dies, and bridges can be connected together in otherpossible configurations, including three-dimensional configurations.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-14 illustrated exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general-purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. Exemplary integrated circuit 1200includes one or more application processor(s) 1205 (e.g., CPUs), atleast one graphics processor 1210, and may additionally include an imageprocessor 1215 and/or a video processor 1220, any of which may be amodular IP core from the same or multiple different design facilities.Integrated circuit 1200 includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I²S/I²C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

FIGS. 13A-13B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments describedherein. FIG. 13A illustrates an exemplary graphics processor 1310 of asystem on a chip integrated circuit that may be fabricated using one ormore IP cores, according to an embodiment. FIG. 13B illustrates anadditional exemplary graphics processor 1340 of a system on a chipintegrated circuit that may be fabricated using one or more IP cores,according to an embodiment. Graphics processor 1310 of FIG. 13A is anexample of a low power graphics processor core. Graphics processor 1340of FIG. 13B is an example of a higher performance graphics processorcore. Each of the graphics processors 1310, 1340 can be variants of thegraphics processor 1210 of FIG. 12.

As shown in FIG. 13A, graphics processor 1310 includes a vertexprocessor 1305 and one or more fragment processor(s) 1315A-1315N (e.g.,1315A, 1315B, 1315C, 1315D, through 1315N-1, and 1315N). Graphicsprocessor 1310 can execute different shader programs via separate logic,such that the vertex processor 1305 is optimized to execute operationsfor vertex shader programs, while the one or more fragment processor(s)1315A-1315N execute fragment (e.g., pixel) shading operations forfragment or pixel shader programs. The vertex processor 1305 performsthe vertex processing stage of the 3D graphics pipeline and generatesprimitives and vertex data. The fragment processor(s) 1315A-1315N usethe primitive and vertex data generated by the vertex processor 1305 toproduce a framebuffer that is displayed on a display device. In oneembodiment, the fragment processor(s) 1315A-1315N are optimized toexecute fragment shader programs as provided for in the OpenGL API,which may be used to perform similar operations as a pixel shaderprogram as provided for in the Direct 3D API.

Graphics processor 1310 additionally includes one or more memorymanagement units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuitinterconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B providefor virtual to physical address mapping for the graphics processor 1310,including for the vertex processor 1305 and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 1325A-1325B. In one embodiment the one or more MMU(s)1320A-1320B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 1205, image processor 1215, and/or video processor 1220 ofFIG. 12, such that each processor 1205-1220 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 1330A-1330B enable graphics processor 1310 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

As shown FIG. 13B, graphics processor 1340 includes the one or moreMMU(s) 1320A-1320B, caches 1325A-1325B, and circuit interconnects1330A-1330B of the graphics processor 1310 of FIG. 13A. Graphicsprocessor 1340 includes one or more shader core(s) 1355A-1355N (e.g.,1455A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N),which provides for a unified shader core architecture in which a singlecore or type or core can execute all types of programmable shader code,including shader program code to implement vertex shaders, fragmentshaders, and/or compute shaders. The exact number of shader corespresent can vary among embodiments and implementations. Additionally,graphics processor 1340 includes an inter-core task manager 1345, whichacts as a thread dispatcher to dispatch execution threads to one or moreshader cores 1355A-1355N and a tiling unit 1358 to accelerate tilingoperations for tile-based rendering, in which rendering operations for ascene are subdivided in image space, for example to exploit localspatial coherence within a scene or to optimize use of internal caches.

FIGS. 14A-14B illustrate additional exemplary graphics processor logicaccording to embodiments described herein. FIG. 14A illustrates agraphics core 1400 that may be included within the graphics processor1210 of FIG. 12, and may be a unified shader core 1355A-1355N as in FIG.13B. FIG. 14B illustrates a highly-parallel general-purpose graphicsprocessing unit 1430 suitable for deployment on a multi-chip module.

As shown in FIG. 14A, the graphics core 1400 includes a sharedinstruction cache 1402, a texture unit 1418, and a cache/shared memory1420 that are common to the execution resources within the graphics core1400. The graphics core 1400 can include multiple slices 1401A-1401N orpartition for each core, and a graphics processor can include multipleinstances of the graphics core 1400. The slices 1401A-1401N can includesupport logic including a local instruction cache 1404A-1404N, a threadscheduler 1406A-1406N, a thread dispatcher 1408A-1408N, and a set ofregisters 1410A. To perform logic operations, the slices 1401A-1401N caninclude a set of additional function units (AFUs 1412A-1412N),floating-point units (FPU 1414A-1414N), integer arithmetic logic units(ALUs 1416-1416N), address computational units (ACU 1413A-1413N),double-precision floating-point units (DPFPU 1415A-1415N), and matrixprocessing units (MPU 1417A-1417N).

Some of the computational units operate at a specific precision. Forexample, the FPUs 1414A-1414N can perform single-precision (32-bit) andhalf-precision (16-bit) floating point operations, while the DPFPUs1415A-1415N perform double precision (64-bit) floating point operations.The ALUs 1416A-1416N can perform variable precision integer operationsat 8-bit, 16-bit, and 32-bit precision, and can be configured for mixedprecision operations. The MPUs 1417A-1417N can also be configured formixed precision matrix operations, including half-precision floatingpoint and 8-bit integer operations. The MPUs 1417-1417N can perform avariety of matrix operations to accelerate machine learning applicationframeworks, including enabling support for accelerated general matrix tomatrix multiplication (GEMM). The AFUs 1412A-1412N can performadditional logic operations not supported by the floating-point orinteger units, including trigonometric operations (e.g., Sine, Cosine,etc.).

As shown in FIG. 14B, a general-purpose processing unit (GPGPU) 1430 canbe configured to enable highly-parallel compute operations to beperformed by an array of graphics processing units. Additionally, theGPGPU 1430 can be linked directly to other instances of the GPGPU tocreate a multi-GPU cluster to improve training speed for particularlydeep neural networks. The GPGPU 1430 includes a host interface 1432 toenable a connection with a host processor. In one embodiment the hostinterface 1432 is a PCI Express interface. However, the host interfacecan also be a vendor specific communications interface or communicationsfabric. The GPGPU 1430 receives commands from the host processor anduses a global scheduler 1434 to distribute execution threads associatedwith those commands to a set of compute clusters 1436A-1436H. Thecompute clusters 1436A-1436H share a cache memory 1438. The cache memory1438 can serve as a higher-level cache for cache memories within thecompute clusters 1436A-1436H.

The GPGPU 1430 includes memory 1434A-1434B coupled with the computeclusters 1436A-1436H via a set of memory controllers 1442A-1442B. Invarious embodiments, the memory 1434A-1434B can include various types ofmemory devices including dynamic random access memory (DRAM) or graphicsrandom access memory, such as synchronous graphics random access memory(SGRAM), including graphics double data rate (GDDR) memory.

In one embodiment the compute clusters 1436A-1436H each include a set ofgraphics cores, such as the graphics core 1400 of FIG. 14A, which caninclude multiple types of integer and floating point logic units thatcan perform computational operations at a range of precisions includingsuited for machine learning computations. For example and in oneembodiment at least a subset of the floating point units in each of thecompute clusters 1436A-1436H can be configured to perform 16-bit or32-bit floating point operations, while a different subset of thefloating point units can be configured to perform 64-bit floating pointoperations.

Multiple instances of the GPGPU 1430 can be configured to operate as acompute cluster. The communication mechanism used by the compute clusterfor synchronization and data exchange varies across embodiments. In oneembodiment the multiple instances of the GPGPU 1430 communicate over thehost interface 1432. In one embodiment the GPGPU 1430 includes an I/Ohub 1439 that couples the GPGPU 1430 with a GPU link 1440 that enables adirect connection to other instances of the GPGPU. In one embodiment theGPU link 1440 is coupled to a dedicated GPU-to-GPU bridge that enablescommunication and synchronization between multiple instances of theGPGPU 1430. In one embodiment the GPU link 1440 couples with a highspeed interconnect to transmit and receive data to other GPGPUs orparallel processors. In one embodiment the multiple instances of theGPGPU 1430 are located in separate data processing systems andcommunicate via a network device that is accessible via the hostinterface 1432. In one embodiment the GPU link 1440 can be configured toenable a connection to a host processor in addition to or as analternative to the host interface 1432.

While the illustrated configuration of the GPGPU 1430 can be configuredto train neural networks, one embodiment provides alternateconfiguration of the GPGPU 1430 that can be configured for deploymentwithin a high performance or low power inferencing platform. In aninferencing configuration the GPGPU 1430 includes fewer of the computeclusters 1436A-1436H relative to the training configuration.Additionally, the memory technology associated with the memory1434A-1434B may differ between inferencing and training configurations,with higher bandwidth memory technologies devoted to trainingconfigurations. In one embodiment the inferencing configuration of theGPGPU 1430 can support inferencing specific instructions. For example,an inferencing configuration can provide support for one or more 8-bitinteger dot product instructions, which are commonly used duringinferencing operations for deployed neural networks

Machine Learning Overview

A machine learning algorithm is an algorithm that can learn based on aset of data. Embodiments of machine learning algorithms can be designedto model high-level abstractions within a data set. For example, imagerecognition algorithms can be used to determine which of severalcategories to which a given input belong; regression algorithms canoutput a numerical value given an input; and pattern recognitionalgorithms can be used to generate translated text or perform text tospeech and/or speech recognition.

An exemplary type of machine learning algorithm is a neural network.There are many types of neural networks; a simple type of neural networkis a feedforward network. A feedforward network may be implemented as anacyclic graph in which the nodes are arranged in layers. Typically, afeedforward network topology includes an input layer and an output layerthat are separated by at least one hidden layer. The hidden layertransforms input received by the input layer into a representation thatis useful for generating output in the output layer. The network nodesare fully connected via edges to the nodes in adjacent layers, but thereare no edges between nodes within each layer. Data received at the nodesof an input layer of a feedforward network are propagated (i.e., “fedforward”) to the nodes of the output layer via an activation functionthat calculates the states of the nodes of each successive layer in thenetwork based on coefficients (“weights”) respectively associated witheach of the edges connecting the layers. Depending on the specific modelbeing represented by the algorithm being executed, the output from theneural network algorithm can take various forms.

Before a machine learning algorithm can be used to model a particularproblem, the algorithm is trained using a training data set. Training aneural network involves selecting a network topology, using a set oftraining data representing a problem being modeled by the network, andadjusting the weights until the network model performs with a minimalerror for all instances of the training data set. For example, during asupervised learning training process for a neural network, the outputproduced by the network in response to the input representing aninstance in a training data set is compared to the “correct” labeledoutput for that instance, an error signal representing the differencebetween the output and the labeled output is calculated, and the weightsassociated with the connections are adjusted to minimize that error asthe error signal is backward propagated through the layers of thenetwork. The network is considered “trained” when the errors for each ofthe outputs generated from the instances of the training data set areminimized.

The accuracy of a machine learning algorithm can be affectedsignificantly by the quality of the data set used to train thealgorithm. The training process can be computationally intensive and mayrequire a significant amount of time on a conventional general-purposeprocessor. Accordingly, parallel processing hardware is used to trainmany types of machine learning algorithms. This is particularly usefulfor optimizing the training of neural networks, as the computationsperformed in adjusting the coefficients in neural networks lendthemselves naturally to parallel implementations. Specifically, manymachine learning algorithms and software applications have been adaptedto make use of the parallel processing hardware within general-purposegraphics processing devices.

FIG. 15 is a generalized diagram of a machine learning software stack1500. A machine learning application 1502 can be configured to train aneural network using a training dataset or to use a trained deep neuralnetwork to implement machine intelligence. The machine learningapplication 1502 can include training and inference functionality for aneural network and/or specialized software that can be used to train aneural network before deployment. The machine learning application 1502can implement any type of machine intelligence including but not limitedto image recognition, mapping and localization, autonomous navigation,speech synthesis, medical imaging, or language translation.

Hardware acceleration for the machine learning application 1502 can beenabled via a machine learning framework 1504. The machine learningframework 1504 can provide a library of machine learning primitives.Machine learning primitives are basic operations that are commonlyperformed by machine learning algorithms. Without the machine learningframework 1504, developers of machine learning algorithms would berequired to create and optimize the main computational logic associatedwith the machine learning algorithm, then re-optimize the computationallogic as new parallel processors are developed. Instead, the machinelearning application can be configured to perform the necessarycomputations using the primitives provided by the machine learningframework 1504. Exemplary primitives include tensor convolutions,activation functions, and pooling, which are computational operationsthat are performed while training a convolutional neural network (CNN).The machine learning framework 1504 can also provide primitives toimplement basic linear algebra subprograms performed by manymachine-learning algorithms, such as matrix and vector operations.

The machine learning framework 1504 can process input data received fromthe machine learning application 1502 and generate the appropriate inputto a compute framework 1506. The compute framework 1506 can abstract theunderlying instructions provided to the GPGPU driver 1508 to enable themachine learning framework 1504 to take advantage of hardwareacceleration via the GPGPU hardware 1510 without requiring the machinelearning framework 1504 to have intimate knowledge of the architectureof the GPGPU hardware 1510. Additionally, the compute framework 1506 canenable hardware acceleration for the machine learning framework 1504across a variety of types and generations of the GPGPU hardware 1510.

Machine Learning Neural Network Implementations

The computing architecture provided by embodiments described herein canbe configured to perform the types of parallel processing that isparticularly suited for training and deploying neural networks formachine learning. A neural network can be generalized as a network offunctions having a graph relationship. As is known in the art, there area variety of types of neural network implementations used in machinelearning. One exemplary type of neural network is the feedforwardnetwork, as previously described.

A second exemplary type of neural network is the Convolutional NeuralNetwork (CNN). A CNN is a specialized feedforward neural network forprocessing data having a known, grid-like topology, such as image data.Accordingly, CNNs are commonly used for compute vision and imagerecognition applications, but they also may be used for other types ofpattern recognition such as speech and language processing. The nodes inthe CNN input layer are organized into a set of “filters” (featuredetectors inspired by the receptive fields found in the retina), and theoutput of each set of filters is propagated to nodes in successivelayers of the network. The computations for a CNN include applying theconvolution mathematical operation to each filter to produce the outputof that filter. Convolution is a specialized kind of mathematicaloperation performed by two functions to produce a third function that isa modified version of one of the two original functions. Inconvolutional network terminology, the first function to the convolutioncan be referred to as the input, while the second function can bereferred to as the convolution kernel. The output may be referred to asthe feature map. For example, the input to a convolution layer can be amultidimensional array of data that defines the various color componentsof an input image. The convolution kernel can be a multidimensionalarray of parameters, where the parameters are adapted by the trainingprocess for the neural network.

Recurrent neural networks (RNNs) are a family of feedforward neuralnetworks that include feedback connections between layers. RNNs enablemodeling of sequential data by sharing parameter data across differentparts of the neural network. The architecture for a RNN includes cycles.The cycles represent the influence of a present value of a variable onits own value at a future time, as at least a portion of the output datafrom the RNN is used as feedback for processing subsequent input in asequence. This feature makes RNNs particularly useful for languageprocessing due to the variable nature in which language data can becomposed.

The figures described below present exemplary feedforward, CNN, and RNNnetworks, as well as describe a general process for respectivelytraining and deploying each of those types of networks. It will beunderstood that these descriptions are exemplary and non-limiting as toany specific embodiment described herein and the concepts illustratedcan be applied generally to deep neural networks and machine learningtechniques in general.

The exemplary neural networks described above can be used to performdeep learning. Deep learning is machine learning using deep neuralnetworks. The deep neural networks used in deep learning are artificialneural networks composed of multiple hidden layers, as opposed toshallow neural networks that include only a single hidden layer. Deeperneural networks are generally more computationally intensive to train.However, the additional hidden layers of the network enable multisteppattern recognition that results in reduced output error relative toshallow machine learning techniques.

Deep neural networks used in deep learning typically include a front-endnetwork to perform feature recognition coupled to a back-end networkwhich represents a mathematical model that can perform operations (e.g.,object classification, speech recognition, etc.) based on the featurerepresentation provided to the model. Deep learning enables machinelearning to be performed without requiring hand crafted featureengineering to be performed for the model. Instead, deep neural networkscan learn features based on statistical structure or correlation withinthe input data. The learned features can be provided to a mathematicalmodel that can map detected features to an output. The mathematicalmodel used by the network is generally specialized for the specific taskto be performed, and different models will be used to perform differenttask.

Once the neural network is structured, a learning model can be appliedto the network to train the network to perform specific tasks. Thelearning model describes how to adjust the weights within the model toreduce the output error of the network. Backpropagation of errors is acommon method used to train neural networks. An input vector ispresented to the network for processing. The output of the network iscompared to the desired output using a loss function and an error valueis calculated for each of the neurons in the output layer. The errorvalues are then propagated backwards until each neuron has an associatederror value which roughly represents its contribution to the originaloutput. The network can then learn from those errors using an algorithm,such as the stochastic gradient descent algorithm, to update the weightsof the of the neural network.

FIG. 16A-16B illustrate an exemplary convolutional neural network. FIG.16A illustrates various layers within a CNN. As shown in FIG. 16A, anexemplary CNN used to model image processing can receive input 1602describing the red, green, and blue (RGB) components of an input image.The input 1602 can be processed by multiple convolutional layers (e.g.,first convolutional layer 1604, second convolutional layer 1606). Theoutput from the multiple convolutional layers may optionally beprocessed by a set of fully connected layers 1608. Neurons in a fullyconnected layer have full connections to all activations in the previouslayer, as previously described for a feedforward network. The outputfrom the fully connected layers 1608 can be used to generate an outputresult from the network. The activations within the fully connectedlayers 1608 can be computed using matrix multiplication instead ofconvolution. Not all CNN implementations are make use of fully connectedlayers 1608. For example, in some implementations the secondconvolutional layer 1606 can generate output for the CNN.

The convolutional layers are sparsely connected, which differs fromtraditional neural network configuration found in the fully connectedlayers 1608. Traditional neural network layers are fully connected, suchthat every output unit interacts with every input unit. However, theconvolutional layers are sparsely connected because the output of theconvolution of a field is input (instead of the respective state valueof each of the nodes in the field) to the nodes of the subsequent layer,as illustrated. The kernels associated with the convolutional layersperform convolution operations, the output of which is sent to the nextlayer. The dimensionality reduction performed within the convolutionallayers is one aspect that enables the CNN to scale to process largeimages.

FIG. 16B illustrates exemplary computation stages within a convolutionallayer of a CNN. Input to a convolutional layer 1612 of a CNN can beprocessed in three stages of a convolutional layer 1614. The threestages can include a convolution stage 1616, a detector stage 1618, anda pooling stage 1620. The convolution layer 1614 can then output data toa successive convolutional layer. The final convolutional layer of thenetwork can generate output feature map data or provide input to a fullyconnected layer, for example, to generate a classification value for theinput to the CNN.

In the convolution stage 1616 performs several convolutions in parallelto produce a set of linear activations. The convolution stage 1616 caninclude an affine transformation, which is any transformation that canbe specified as a linear transformation plus a translation. Affinetransformations include rotations, translations, scaling, andcombinations of these transformations. The convolution stage computesthe output of functions (e.g., neurons) that are connected to specificregions in the input, which can be determined as the local regionassociated with the neuron. The neurons compute a dot product betweenthe weights of the neurons and the region in the local input to whichthe neurons are connected. The output from the convolution stage 1616defines a set of linear activations that are processed by successivestages of the convolutional layer 1614.

The linear activations can be processed by a detector stage 1618. In thedetector stage 1618, each linear activation is processed by a non-linearactivation function. The non-linear activation function increases thenonlinear properties of the overall network without affecting thereceptive fields of the convolution layer. Several types of non-linearactivation functions may be used. One particular type is the rectifiedlinear unit (ReLU), which uses an activation function defined asƒ(x)=max(0, x), such that the activation is thresholded at zero.

The pooling stage 1620 uses a pooling function that replaces the outputof the second convolutional layer 1606 with a summary statistic of thenearby outputs. The pooling function can be used to introducetranslation invariance into the neural network, such that smalltranslations to the input do not change the pooled outputs. Invarianceto local translation can be useful in scenarios where the presence of afeature in the input data is more important than the precise location ofthe feature. Various types of pooling functions can be used during thepooling stage 1620, including max pooling, average pooling, and 12-normpooling. Additionally, some CNN implementations do not include a poolingstage. Instead, such implementations substitute and additionalconvolution stage having an increased stride relative to previousconvolution stages.

The output from the convolutional layer 1614 can then be processed bythe next layer 1622. The next layer 1622 can be an additionalconvolutional layer or one of the fully connected layers 1608. Forexample, the first convolutional layer 1604 of FIG. 16A can output tothe second convolutional layer 1606, while the second convolutionallayer can output to a first layer of the fully connected layers 1608.

FIG. 17 illustrates an exemplary recurrent neural network. In arecurrent neural network (RNN), the previous state of the networkinfluences the output of the current state of the network. RNNs can bebuilt in a variety of ways using a variety of functions. The use of RNNsgenerally revolves around using mathematical models to predict thefuture based on a prior sequence of inputs. For example, an RNN may beused to perform statistical language modeling to predict an upcomingword given a previous sequence of words. The illustrated RNN 1700 can bedescribed as having an input layer 1702 that receives an input vector,hidden layers 1704 to implement a recurrent function, a feedbackmechanism 1705 to enable a ‘memory’ of previous states, and an outputlayer 1706 to output a result. The RNN 1700 operates based ontime-steps. The state of the RNN at a given time step is influencedbased on the previous time step via the feedback mechanism 1705. For agiven time step, the state of the hidden layers 1704 is defined by theprevious state and the input at the current time step. An initial input(x₁) at a first time step can be processed by the hidden layer 1704. Asecond input (x₂) can be processed by the hidden layer 1704 using stateinformation that is determined during the processing of the initialinput (x₁). A given state can be computed as s_(t)=ƒ(Ux_(t)+Ws_(t-1)),where U and W are parameter matrices. The function ƒ is generally anonlinearity, such as the hyperbolic tangent function (Tanh) or avariant of the rectifier function ƒ(x)=max(0, x). However, the specificmathematical function used in the hidden layers 1704 can vary dependingon the specific implementation details of the RNN 1700.

In addition to the basic CNN and RNN networks described, variations onthose networks may be enabled. One example RNN variant is the longshort-term memory (LSTM) RNN. LSTM RNNs are capable of learninglong-term dependencies that may be necessary for processing longersequences of language. A variant on the CNN is a convolutional deepbelief network, which has a structure similar to a CNN and is trained ina manner similar to a deep belief network. A deep belief network (DBN)is a generative neural network that is composed of multiple layers ofstochastic (random) variables. DBNs can be trained layer-by-layer usinggreedy unsupervised learning. The learned weights of the DBN can then beused to provide pre-train neural networks by determining an optimalinitial set of weights for the neural network.

FIG. 18 illustrates training and deployment of a deep neural network.Once a given network has been structured for a task the neural networkis trained using a training dataset 1802. Various training frameworkshave been developed to enable hardware acceleration of the trainingprocess. For example, the machine learning framework 1504 of FIG. 15 maybe configured as a training framework 1804. The training framework 1804can hook into an untrained neural network 1806 and enable the untrainedneural net to be trained using the parallel processing resourcesdescribed herein to generate a trained neural network 1808. To start thetraining process the initial weights may be chosen randomly or bypre-training using a deep belief network. The training cycle then beperformed in either a supervised or unsupervised manner.

Supervised learning is a learning method in which training is performedas a mediated operation, such as when the training dataset 1802 includesinput paired with the desired output for the input, or where thetraining dataset includes input having known output and the output ofthe neural network is manually graded. The network processes the inputsand compares the resulting outputs against a set of expected or desiredoutputs. Errors are then propagated back through the system. Thetraining framework 1804 can adjust to adjust the weights that controlthe untrained neural network 1806. The training framework 1804 canprovide tools to monitor how well the untrained neural network 1806 isconverging towards a model suitable to generating correct answers basedon known input data. The training process occurs repeatedly as theweights of the network are adjusted to refine the output generated bythe neural network. The training process can continue until the neuralnetwork reaches a statistically desired accuracy associated with atrained neural network 1808. The trained neural network 1808 can then bedeployed to implement any number of machine learning operations.

Unsupervised learning is a learning method in which the network attemptsto train itself using unlabeled data. Thus, for unsupervised learningthe training dataset 1802 will include input data without any associatedoutput data. The untrained neural network 1806 can learn groupingswithin the unlabeled input and can determine how individual inputs arerelated to the overall dataset. Unsupervised training can be used togenerate a self-organizing map, which is a type of trained neuralnetwork 1807 capable of performing operations useful in reducing thedimensionality of data. Unsupervised training can also be used toperform anomaly detection, which allows the identification of datapoints in an input dataset that deviate from the normal patterns of thedata.

Variations on supervised and unsupervised training may also be employed.Semi-supervised learning is a technique in which in the training dataset1802 includes a mix of labeled and unlabeled data of the samedistribution. Incremental learning is a variant of supervised learningin which input data is continuously used to further train the model.Incremental learning enables the trained neural network 1808 to adapt tothe new data 1812 without forgetting the knowledge instilled within thenetwork during initial training.

Whether supervised or unsupervised, the training process forparticularly deep neural networks may be too computationally intensivefor a single compute node. Instead of using a single compute node, adistributed network of computational nodes can be used to accelerate thetraining process.

FIG. 19 is a block diagram illustrating distributed learning.Distributed learning is a training model that uses multiple distributedcomputing nodes to perform supervised or unsupervised training of aneural network. The distributed computational nodes can each include oneor more host processors and one or more of the general-purposeprocessing nodes. As illustrated, distributed learning can be performedmodel parallelism 1902, data parallelism 1904, or a combination of modeland data parallelism 1904.

In model parallelism 1902, different computational nodes in adistributed system can perform training computations for different partsof a single network. For example, each layer of a neural network can betrained by a different processing node of the distributed system. Thebenefits of model parallelism include the ability to scale toparticularly large models. Splitting the computations associated withdifferent layers of the neural network enables the training of verylarge neural networks in which the weights of all layers would not fitinto the memory of a single computational node. In some instances, modelparallelism can be particularly useful in performing unsupervisedtraining of large neural networks.

In data parallelism 1904, the different nodes of the distributed networkhave a complete instance of the model and each node receives a differentportion of the data. The results from the different nodes are thencombined. While different approaches to data parallelism are possible,data parallel training approaches all require a technique of combiningresults and synchronizing the model parameters between each node.Exemplary approaches to combining data include parameter averaging andupdate based data parallelism. Parameter averaging trains each node on asubset of the training data and sets the global parameters (e.g.,weights, biases) to the average of the parameters from each node.Parameter averaging uses a central parameter server that maintains theparameter data. Update based data parallelism is similar to parameteraveraging except that instead of transferring parameters from the nodesto the parameter server, the updates to the model are transferred.Additionally, update based data parallelism can be performed in adecentralized manner, where the updates are compressed and transferredbetween nodes.

Combined model and data parallelism 1906 can be implemented, forexample, in a distributed system in which each computational nodeincludes multiple GPUs. Each node can have a complete instance of themodel with separate GPUs within each node are used to train differentportions of the model.

Distributed training has increased overhead relative to training on asingle machine. However, the parallel processors and GPGPUs describedherein can each implement various techniques to reduce the overhead ofdistributed training, including techniques to enable high bandwidthGPU-to-GPU data transfer and accelerated remote data synchronization.

Exemplary Machine Learning Applications

Machine learning can be applied to solve a variety of technologicalproblems, including but not limited to computer vision, autonomousdriving and navigation, speech recognition, and language processing.Computer vision has traditionally been one of the most active researchareas for machine learning applications. Applications of computer visionrange from reproducing human visual abilities, such as recognizingfaces, to creating new categories of visual abilities. For example,computer vision applications can be configured to recognize sound wavesfrom the vibrations induced in objects visible in a video. Parallelprocessor accelerated machine learning enables computer visionapplications to be trained using significantly larger training datasetthan previously feasible and enables inferencing systems to be deployedusing low power parallel processors.

Parallel processor accelerated machine learning has autonomous drivingapplications including lane and road sign recognition, obstacleavoidance, navigation, and driving control. Accelerated machine learningtechniques can be used to train driving models based on datasets thatdefine the appropriate responses to specific training input. Theparallel processors described herein can enable rapid training of theincreasingly complex neural networks used for autonomous drivingsolutions and enables the deployment of low power inferencing processorsin a mobile platform suitable for integration into autonomous vehicles.

Parallel processor accelerated deep neural networks have enabled machinelearning approaches to automatic speech recognition (ASR). ASR includesthe creation of a function that computes the most probable linguisticsequence given an input acoustic sequence. Accelerated machine learningusing deep neural networks have enabled the replacement of the hiddenMarkov models (HMMs) and Gaussian mixture models (GMMs) previously usedfor ASR.

Parallel processor accelerated machine learning can also be used toaccelerate natural language processing. Automatic learning procedurescan make use of statistical inference algorithms to produce models thatare robust to erroneous or unfamiliar input. Exemplary natural languageprocessor applications include automatic machine translation betweenhuman languages.

The parallel processing platforms used for machine learning can bedivided into training platforms and deployment platforms. Trainingplatforms are generally highly parallel and include optimizations toaccelerate multi-GPU single node training and multi-node, multi-GPUtraining, while deployed machine learning (e.g., inferencing) platformsgenerally include lower power parallel processors suitable for use inproducts such as cameras, autonomous robots, and autonomous vehicles.

FIG. 20 illustrates one embodiment of a computing device 2000 employingan accelerator 2010. Computing device 2000 (e.g., smart wearabledevices, virtual reality (VR) devices, head-mounted display (HMDs),mobile computers, Internet of Things (IoT) devices, laptop computers,desktop computers, server computers, etc.) may be the same as dataprocessing system 100 of FIG. 1 and accordingly, for brevity, clarity,and ease of understanding, many of the details stated above withreference to FIGS. 1-19 are not further discussed or repeated hereafter.As illustrated, in one embodiment, computing device 2000 is shown ashosting an accelerator 2010.

Although illustrated as a separate component, other embodiments mayfeature accelerator 2010 being hosted by graphics processing unit (GPU)2014. In other embodiments, accelerator 2010 may be hosted by or part offirmware of central processing unit (“CPU” or “application processor”)2012. For brevity, clarity, and ease of understanding, throughout therest of this document, accelerator 2010 may be discussed as a separatecomponent; however, embodiments are not limited as such.

In yet another embodiment, accelerator mechanism 2010 may be partiallyand simultaneously hosted by multiple components of computing device2000, such as one or more of graphics driver 616, GPU 2014, GPUfirmware, CPU 2012, CPU firmware, operating system 2006, and/or thelike. It is contemplated that accelerator 2010 or one or more of theircomponents may be implemented as hardware, software, and/or firmware.

Throughout the document, terms like “graphics domain” may be referencedinterchangeably with “graphics processing unit”, “graphics processor”,or simply “GPU” and similarly, “CPU domain” or “host domain” may bereferenced interchangeably with “computer processing unit”, “applicationprocessor”, or simply “CPU”.

Computing device 2000 may include any number and type of communicationdevices, such as large computing systems, such as server computers,desktop computers, etc., and may further include set-top boxes (e.g.,Internet-based cable television set-top boxes, etc.), global positioningsystem (GPS)-based devices, etc. Computing device 2000 may includemobile computing devices serving as communication devices, such ascellular phones including smartphones, personal digital assistants(PDAs), tablet computers, laptop computers, e-readers, smarttelevisions, television platforms, wearable devices (e.g., glasses,watches, bracelets, smartcards, jewelry, clothing items, etc.), mediaplayers, etc. For example, in one embodiment, computing device 2000 mayinclude a mobile computing device employing a computer platform hostingan integrated circuit (“IC”), such as system on a chip (“SoC” or “SOC”),integrating various hardware and/or software components of computingdevice 2000 on a single chip.

As illustrated, in one embodiment, computing device 2000 may include anynumber and type of hardware and/or software components, such as (withoutlimitation) GPU 2014, graphics driver (also referred to as “GPU driver”,“graphics driver logic”, “driver logic”, user-mode driver (UMD), UMD,user-mode driver framework (UMDF), UMDF, or simply “driver”) 616, CPU2012, memory 2008, network devices, drivers, or the like, as well asinput/output (I/O) sources 2004, such as touchscreens, touch panels,touch pads, virtual or regular keyboards, virtual or regular mice,ports, connectors, etc.

Computing device 2000 may include operating system (OS) 2006 serving asan interface between hardware and/or physical resources of the computerdevice 2000 and a user. It is contemplated that CPU 2012 may include oneor more processors, such as processor(s) 102 of FIG. 1, while GPU 2014may include one or more graphics processors (or multiprocessors).

It is to be noted that terms like “node”, “computing node”, “server”,“server device”, “cloud computer”, “cloud server”, “cloud servercomputer”, “machine”, “host machine”, “device”, “computing device”,“computer”, “computing system”, and the like, may be usedinterchangeably throughout this document. It is to be further noted thatterms like “application”, “software application”, “program”, “softwareprogram”, “package”, “software package”, and the like, may be usedinterchangeably throughout this document. Also, terms like “job”,“input”, “request”, “message”, and the like, may be used interchangeablythroughout this document.

It is contemplated and as further described with reference to FIGS.1-14, some processes of the graphics pipeline as described above areimplemented in software, while the rest are implemented in hardware. Agraphics pipeline may be implemented in a graphics coprocessor design,where CPU 2012 is designed to work with GPU 2014 which may be includedin or co-located with CPU 2012. In one embodiment, GPU 2014 may employany number and type of conventional software and hardware logic toperform the conventional functions relating to graphics rendering aswell as novel software and hardware logic to execute any number and typeof instructions.

As aforementioned, memory 2008 may include a random access memory (RAM)comprising application database having object information. A memorycontroller hub, such as memory hub 105 of FIG. 1, may access data in theRAM and forward it to GPU 2014 for graphics pipeline processing. RAM mayinclude double data rate RAM (DDR RAM), extended data output RAM (EDORAM), etc. CPU 2012 interacts with a hardware graphics pipeline to sharegraphics pipelining functionality.

Processed data is stored in a buffer in the hardware graphics pipeline,and state information is stored in memory 2008. The resulting image isthen transferred to I/O sources 2004, such as a display component fordisplaying of the image. It is contemplated that the display device maybe of various types, such as Cathode Ray Tube (CRT), Thin FilmTransistor (TFT), Liquid Crystal Display (LCD), Organic Light EmittingDiode (OLED) array, etc., to display information to a user.

Memory 2008 may comprise a pre-allocated region of a buffer (e.g., framebuffer); however, it should be understood by one of ordinary skill inthe art that the embodiments are not so limited, and that any memoryaccessible to the lower graphics pipeline may be used. Computing device2000 may further include input/output (I/O) control hub (ICH) 107 asreferenced in FIG. 1, as one or more I/O sources 2004, etc.

CPU 2012 may include one or more processors to execute instructions inorder to perform whatever software routines the computing systemimplements. The instructions frequently involve some sort of operationperformed upon data. Both data and instructions may be stored in systemmemory 2008 and any associated cache. Cache is typically designed tohave shorter latency times than system memory 2008; for example, cachemight be integrated onto the same silicon chip(s) as the processor(s)and/or constructed with faster static RAM (SRAM) cells whilst the systemmemory 2008 might be constructed with slower dynamic RAM (DRAM) cells.By tending to store more frequently used instructions and data in thecache as opposed to the system memory 2008, the overall performanceefficiency of computing device 2000 improves. It is contemplated that insome embodiments, GPU 2014 may exist as part of CPU 2012 (such as partof a physical CPU package) in which case, memory 2008 may be shared byCPU 2012 and GPU 2014 or kept separated.

System memory 2008 may be made available to other components within thecomputing device 2000. For example, any data (e.g., input graphics data)received from various interfaces to the computing device 2000 (e.g.,keyboard and mouse, printer port, Local Area Network (LAN) port, modemport, etc.) or retrieved from an internal storage element of thecomputer device 2000 (e.g., hard disk drive) are often temporarilyqueued into system memory 2008 prior to being operated upon by the oneor more processor(s) in the implementation of a software program.Similarly, data that a software program determines should be sent fromthe computing device 2000 to an outside entity through one of thecomputing system interfaces, or stored into an internal storage element,is often temporarily queued in system memory 2008 prior to its beingtransmitted or stored.

Further, for example, an ICH may be used for ensuring that such data isproperly passed between the system memory 2008 and its appropriatecorresponding computing system interface (and internal storage device ifthe computing system is so designed) and may have bi-directionalpoint-to-point links between itself and the observed 110 sources/devices2004. Similarly, platform control hub (PCH) may be used for managing thevarious contending requests for system memory 2008 accesses amongst CPU2012 and GPU 2014, interfaces and internal storage elements that mayproximately arise in time with respect to one another.

I/O sources 2004 may include one or more I/O devices that areimplemented for transferring data to and/or from computing device 2000(e.g., a networking adapter); or, for a large scale non-volatile storagewithin computing device 2000 (e.g., hard disk drive). User input device,including alphanumeric and other keys, may be used to communicateinformation and command selections to GPU 2014. Another type of userinput device is cursor control, such as a mouse, a trackball, atouchscreen, a touchpad, or cursor direction keys to communicatedirection information and command selections to GPU 2014 and to controlcursor movement on the display device. Camera and microphone arrays ofcomputer device 2000 may be employed to observe gestures, record audioand video and to receive and transmit visual and audio commands.

Computing device 2000 may further include network interface(s) toprovide access to a network, such as a LAN, a wide area network (WAN), ametropolitan area network (MAN), a personal area network (PAN),Bluetooth, a cloud network, a mobile network (e.g., 3rd Generation (3G),4th Generation (4G), etc.), an intranet, the Internet, etc. Networkinterface(s) may include, for example, a wireless network interfacehaving antenna, which may represent one or more antenna(e). Networkinterface(s) may also include, for example, a wired network interface tocommunicate with remote devices via network cable, which may be, forexample, an Ethernet cable, a coaxial cable, a fiber optic cable, aserial cable, or a parallel cable.

Network interface(s) may provide access to a LAN, for example, byconforming to IEEE 802.11b and/or IEEE 802.11g standards, and/or thewireless network interface may provide access to a personal areanetwork, for example, by conforming to Bluetooth standards. Otherwireless network interfaces and/or protocols, including previous andsubsequent versions of the standards, may also be supported. In additionto, or instead of, communication via the wireless LAN standards, networkinterface(s) may provide wireless communication using, for example, TimeDivision, Multiple Access (TDMA) protocols, Global Systems for MobileCommunications (GSM) protocols, Code Division, Multiple Access (CDMA)protocols, and/or any other type of wireless communications protocols.

Network interface(s) may include one or more communication interfaces,such as a modem, a network interface card, or other well-known interfacedevices, such as those used for coupling to the Ethernet, token ring, orother types of physical wired or wireless attachments for purposes ofproviding a communication link to support a LAN or a WAN, for example.In this manner, the computer system may also be coupled to a number ofperipheral devices, clients, control surfaces, consoles, or servers viaa conventional network infrastructure, including an Intranet or theInternet, for example.

It is to be appreciated that a lesser or more equipped system than theexample described above may be preferred for certain implementations.Therefore, the configuration of computing device 2000 may vary fromimplementation to implementation depending upon numerous factors, suchas price constraints, performance requirements, technologicalimprovements, or other circumstances. Examples of the electronic deviceor computer system 2000 may include (without limitation) a mobiledevice, a personal digital assistant, a mobile computing device, asmartphone, a cellular telephone, a handset, a one-way pager, a two-waypager, a messaging device, a computer, a personal computer (PC), adesktop computer, a laptop computer, a notebook computer, a handheldcomputer, a tablet computer, a server, a server array or server farm, aweb server, a network server, an Internet server, a work station, amini-computer, a main frame computer, a supercomputer, a networkappliance, a web appliance, a distributed computing system,multiprocessor systems, processor-based systems, consumer electronics,programmable consumer electronics, television, digital television, settop box, wireless access point, base station, subscriber station, mobilesubscriber center, radio network controller, router, hub, gateway,bridge, switch, machine, or combinations thereof.

Embodiments may be implemented as any or a combination of: one or moremicrochips or integrated circuits interconnected using a parentboard,hardwired logic, software stored by a memory device and executed by amicroprocessor, firmware, an application specific integrated circuit(ASIC), and/or a field programmable gate array (FPGA). The term “logic”may include, by way of example, software or hardware and/or combinationsof software and hardware.

Embodiments may be provided, for example, as a computer program productwhich may include one or more machine-readable media having storedthereon machine-executable instructions that, when executed by one ormore machines such as a computer, network of computers, or otherelectronic devices, may result in the one or more machines carrying outoperations in accordance with embodiments described herein. Amachine-readable medium may include, but is not limited to, floppydiskettes, optical disks, CD-ROMs (Compact Disc-Read Only Memories), andmagneto-optical disks, ROMs, RAMs, EPROMs (Erasable Programmable ReadOnly Memories), EEPROMs (Electrically Erasable Programmable Read OnlyMemories), magnetic or optical cards, flash memory, or other type ofmedia/machine-readable medium suitable for storing machine-executableinstructions.

Moreover, embodiments may be downloaded as a computer program product,wherein the program may be transferred from a remote computer (e.g., aserver) to a requesting computer (e.g., a client) by way of one or moredata signals embodied in and/or modulated by a carrier wave or otherpropagation medium via a communication link (e.g., a modem and/ornetwork connection).

As discussed above, conventional 2-D SIMD grids cannot easily performhardware intensive non-linear (NL) functions. Specifically, deeplearning topologies targeted towards neural machine translation (NMT)applications employ NL activation functions (e.g., sigmoid and tanh)after every layer. However, conventional systems require the CNN/GEMMoutputs to be routed to memory and a core for a software implementation,resulting in unnecessary power/performance penalties.

According to one embodiment, accelerator 2010 provides a hardwarearchitecture having a SIMD compute grid architecture to implement NLfunctions on the same compute grid implementing neural networks (e.g.,GEMM/CNN). FIG. 21 illustrates one embodiment of an accelerator 2010. Asshown in FIG. 21, accelerator 2010 includes a compute grid having anarray of tiles 2100 (e.g., 2100(a)-(n)) coupled to input memory 2120. Inone embodiment, each tile 2100 includes processing elements 2105 (e.g.,2105(a)-(n)) to perform computations. Additionally, each tile 2100includes weight buffers 2108 and an output memory 2110.

According to one embodiment, two broadcasted inputs (e.g., operand1 andoperand2) are received for both CNN and GEMM. In such an embodiment, PEs2105 share input operand1, while tiles 2100 share operand2. Thisbroadcast of inputs allows minimum data movement with N² computeoperations to be performed per every 2N elements that are fetched, whereN is the size of the compute grid in X or Y direction.

In one embodiment, accelerator 2010 includes 32 tiles, with each tilehaving a fixed number (e.g., 8) PEs 2105. In such an embodiment, each PE2105 includes a 2 stage processing pipeline capable of handling multipledata types (e.g., INT8/FP16). FIG. 22 illustrates one embodiment of a PE2105. As shown in FIG. 22, PE 2105 includes a first stage (STAGE1)including a multiplier 2210 and a second stage (STAGE2) including anaccumulator 2220.

According to one embodiment, accelerator 2010 performs piecewise linear(PWL) approximations of monotonous, saturating NL functions. In such anembodiment, the PWL equations include:

Y=m _(i)(x−x ₁)+c _(i), where x _(i) , m _(i) and c _(i) vary across thelinear segments.

For expansion into accelerator 2010, the above equation is expanded andcomputed in two steps as:

Y=(m _(i) x−m _(i) x _(i))+c _(i)

However prior to implementation of accelerator 2010 to perform the PWLfunction to process input data, an offline process is performed. In oneembodiment, the offline process involves performing simulations offunction topologies and workloads to determine a dynamic range overwhich input data is received. In such an embodiment, an optimal numberof sample (or tap) points is then determined by dividing the range intonon-uniform intervals (x_(i)). Subsequently, a slope (m_(i)) andintercept (c_(i)) may be computed for each interval. Once completed,accelerator 2010 is programmed with m_(i)x_(i), m_(i) and c_(i) for eachinterval. FIG. 23 is a graph of one embodiment of PWL approximation with8 intervals (e.g., x₀-x₇).

Once programmed, accelerator 2010 is implemented to perform PWLapproximations. In one embodiment, an N Tap PWL implementation includesa Look-Up Table (LUT) having 3*N parameters to store m_(i)x_(i), m_(i)and c_(i) values. Thus for an 8 tap embodiment, 24 parameter lookuptable is implemented. In a further embodiment, the LUT values(m_(i)x_(i), m_(i) and c_(i)) are broadcast to the accelerator 2010compute grid.

FIG. 24 is a flow diagram illustrating one embodiment of a process forperforming neural network and NL functions at accelerator 2010. Atprocessing block 2410, the neural network (e.g., CNN/GEMM) computationsare executed. At processing block 2420, final values (e.g., pixelvalues) are stored in the local output buffer. At processing block 2430,NL layer computations are performed.

In one embodiment, the NL layer is performed by each PE 2105 reading thepixel value (X) from the buffer and computing m_(i)*X in STAGE1multiplier 2210. Subsequently STAGE2 accumulator 2220 computesm_(i)*X−m_(i)*x_(i) and writes conditionally into the accumulatorregisters based on a value of a sign enable bit. Further, the additionwith c_(i) is performed in cycle 2 and the write to accumulator isconditional based on the sign enable bit from cycle. In one embodiment,y=symmetry value−y is computed for negative inputs. In a furtherembodiment, SIGM ex: f(−x)=1−f(x))

FIG. 25 is flow diagram illustrating one embodiment of a process forperforming a NL computation at a PE 2105. At processing block 2510, aninput (X) is received at the PE 2105. At processing block 2510,m_(i)*X−m_(i)*x_(i) is computed at a first processing cycle (e.g.,Cycle 1) of PE 2105. FIG. 26A illustrates Cycle 1 at PE 2105. As shownin FIG. 26A, m_(i) and X are received at the STAGE1 multiplier, whichcomputes m_(i)*X. According to one embodiment, the first iteration at PE2105 uses i=0 since the interval at which X is located is unknown. Thus,the multiplier computes m₀*X and forwards the result to the STAGE2accumulator.

The accumulator also receives the value for m₀*x₀ for the computation ofm₀*X−m₀*x₀. In one embodiment, the accumulator saves the sign of thecomputation by setting a value of the sign enable bit. In such anembodiment an active (e.g., logical 1) bit value indicates that anegative sign value, while a de-active (e.g., logical 0) bit valueindicates that a positive sign value.

At processing block 2530, (m₀*X−m₀*x₀)+co is computed at a second cycle(e.g., Cycle 2) of PE 2105. FIG. 26B illustrates Cycle 2 at PE 2105. Asshown in FIG. 26B, the accumulator receives m₀*X−m₀*x₀ and c₀ andperforms the computation. At decision block 2540, a determination asmade as to whether the sign is positive. According to one embodiment, Xdoes not fall in a current interval (i) if X>x_(i) has a positive sign.Thus, for the interval 0 computation the sign is positive if X>x₀.

Upon a determination at decision block 2540 that the sign enable bitindicates that the sign is negative, the computation value of(m₀*X−m₀*x₀)+c₀ is saved as a PWL approximation, processing block 2550.However, upon a determination that the sign is positive, control isreturned to processing blocks 2520-2530 where the computations arerepeated for the next interval (e.g., i=1). In one embodiment, theprocess is repeated for each interval until the sign the changes frompositive to negative. Referring back to FIG. 23, the value for X isshown as being somewhere between interval 2 and 3. Thus, in thisembodiment, the value of (m₃*X-m₃*x₃)+c₃ is saved.

The above-described accelerator provides an effective re-use of SIMDgrid compute resources, and higher throughput, for non-linearoperations, which results in opportunities to fuse with other neuralnetwork layers.

The foregoing description and drawings are to be regarded in anillustrative rather than a restrictive sense. Persons skilled in the artwill understand that various modifications and changes may be made tothe embodiments described herein without departing from the broaderspirit and scope of the invention as set forth in the appended claims.

Some embodiments pertain to Example 1 that includes an apparatus tofacilitate execution of non-linear functions operations comprisingaccelerator circuitry, including a compute grid having a plurality ofprocessing elements to execute neural network computations, store valuesresulting from the neural network computations, and perform piecewiselinear (PWL) approximations of one or more non-linear functions usingthe stored values as input data.

Example 2 includes the subject matter of Example 1, further comprisingone or more lookup tables (LUTs) to store a plurality of non-linearparameter values for the PWL approximations.

Example 3 includes the subject matter of Examples 1 and 2, wherein eachof the plurality of processing elements comprises a first stageincluding a multiplier to perform a multiplication operation of an inputdata value and a first interval version of a first parameter valueduring a first processing cycle of a PWL approximation and a secondstage including an accumulator to perform a subtraction operation of afirst interval version of a second parameter from a result of themultiplication operation.

Example 4 includes the subject matter of Examples 1-3, wherein theaccumulator sets an enable bit indicating a sign of the result of thesubtraction operation.

Example 5 includes the subject matter of Examples 1-4, wherein theaccumulator performs an addition operation of a first interval versionof a third parameter and the result of the subtraction operation duringa second processing cycle of the PWL approximation.

Example 6 includes the subject matter of Examples 1-5, wherein adetermination is made as to whether the enable bit indicates that thesign of the result of the subtraction operation has a first value.

Example 7 includes the subject matter of Examples 1-6, wherein themultiplier performs a second multiplication operation of the input datavalue and a second interval version of the first parameter value duringa third processing cycle of a PWL approximation upon a determinationthat the enable bit indicates that the has the first value, and theaccumulator performs a second subtraction operation of a second intervalversion of the second parameter from a result of the secondmultiplication operation.

Example 8 includes the subject matter of Examples 1-7, wherein a resultof the addition operation is saved as the PWL approximation upon adetermination that the sign has a second value.

Some embodiments pertain to Example 9 that includes a method tofacilitate execution of non-linear functions operations, comprising:accelerator circuitry, including executing neural network computationsat a compute grid having a plurality of processing element, storingvalues resulting from the neural network computations and performingpiecewise linear (PWL) approximations of one or more non-linearfunctions using the stored values as input data.

Example 10 includes the subject matter of Example 9, wherein performingthe PWL approximations comprises performing a first processing cycle,including performing a multiplication operation to multiply an inputdata value and a first interval version of a first parameter value,performing a subtraction operation of a first interval version of asecond parameter from the result of the multiplication operation andsetting an enable bit indicating a sign of the result of the subtractionoperation.

Example 11 includes the subject matter of Examples 9 and 10, furthercomprising performing a second processing cycle, including performing anaddition operation of a first interval version of a third parameter andthe result of the subtraction operation during a second processing cycleof the PWL approximation.

Example 12 includes the subject matter of Examples 9-11, furthercomprising determining whether the enable bit indicates that the sign ofthe result of the subtraction operation has a first value.

Example 13 includes the subject matter of Examples 9-12, furthercomprising performing a third processing cycle, including performing asecond multiplication operation of the input data value and a secondinterval version of the first parameter value upon a determination thatthe enable bit indicates that the has the first value and performing asecond subtraction operation of a second interval version of the secondparameter from the result of the second multiplication operation.

Example 14 includes the subject matter of Examples 9-13, furthercomprising saving a result of the addition operation upon adetermination that the sign has a second value.

Some embodiments pertain to Example 15 that includes an acceleratorcomprising one or more memory devices to store one or more one or morelookup tables (LUTs), and a compute grid having a plurality of aplurality of tiles, each including a plurality of processing elements toexecute neural network computations, store values resulting from theneural network computations, and perform piecewise linear (PWL)approximations of one or more non-linear functions using the storedvalues as input data and non-linear parameter values stored in the oneor more LUTs.

Example 16 includes the subject matter of Example 15, wherein each ofthe plurality of processing elements comprises a first stage including amultiplier to perform a multiplication operation of an input data valueand a first interval version of a first parameter value during a firstprocessing cycle of a PWL approximation and a second stage including anaccumulator to perform a subtraction operation of a first intervalversion of a second parameter from a result of the multiplicationoperation.

Example 17 includes the subject matter of Examples 15 and 16, whereinthe accumulator sets an enable bit indicating a sign of the result ofthe subtraction operation.

Example 18 includes the subject matter of Examples 15-17, wherein theaccumulator performs an addition operation of a first interval versionof a third parameter and the result of the subtraction operation duringa second processing cycle of the PWL approximation.

Example 19 includes the subject matter of Examples 15-18, wherein adetermination is made as to whether the enable bit indicates that thesign of the result of the subtraction operation has a first value.

Example 20 includes the subject matter of Examples 15-19, wherein themultiplier performs a second multiplication operation of the input datavalue and a second interval version of the first parameter value duringa third processing cycle of a PWL approximation upon a determinationthat the enable bit indicates that the has the first value, and theaccumulator performs a second subtraction operation of a second intervalversion of the second parameter from a result of the secondmultiplication operation.

Example 21 includes the subject matter of Examples 15-20, wherein aresult of the addition operation is saved as the PWL approximation upona determination that the sign has a second value.

The foregoing description and drawings are to be regarded in anillustrative rather than a restrictive sense. Persons skilled in the artwill understand that various modifications and changes may be made tothe embodiments described herein without departing from the broaderspirit and scope of the invention as set forth in the appended claims.

What is claimed is:
 1. An apparatus to facilitate execution ofnon-linear functions operations comprising accelerator circuitry,including: a compute grid having a plurality of processing elements toexecute neural network computations, store values resulting from theneural network computations, and perform piecewise linear (PWL)approximations of one or more non-linear functions using the storedvalues as input data.
 2. The apparatus of claim 1, further comprisingone or more lookup tables (LUTs) to store a plurality of non-linearparameter values for the PWL approximations.
 3. The apparatus of claim2, wherein each of the plurality of processing elements comprises: afirst stage including a multiplier to perform a multiplication operationof an input data value and a first interval version of a first parametervalue during a first processing cycle of a PWL approximation; and asecond stage including an accumulator to perform a subtraction operationof a first interval version of a second parameter from a result of themultiplication operation.
 4. The apparatus of claim 3, wherein theaccumulator sets an enable bit indicating a sign of the result of thesubtraction operation.
 5. The apparatus of claim 4, wherein theaccumulator performs an addition operation of a first interval versionof a third parameter and the result of the subtraction operation duringa second processing cycle of the PWL approximation.
 6. The apparatus ofclaim 5, wherein a determination is made as to whether the enable bitindicates that the sign of the result of the subtraction operation has afirst value.
 7. The apparatus of claim 6, wherein the multiplierperforms a second multiplication operation of the input data value and asecond interval version of the first parameter value during a thirdprocessing cycle of a PWL approximation upon a determination that theenable bit indicates that the has the first value, and the accumulatorperforms a second subtraction operation of a second interval version ofthe second parameter from a result of the second multiplicationoperation.
 8. The apparatus of claim 6, wherein a result of the additionoperation is saved as the PWL approximation upon a determination thatthe sign has a second value.
 9. A method to facilitate execution ofnon-linear functions operations, comprising: accelerator circuitry,including: executing neural network computations at a compute gridhaving a plurality of processing element; storing values resulting fromthe neural network computations; and performing piecewise linear (PWL)approximations of one or more non-linear functions using the storedvalues as input data.
 10. The method of claim 9, wherein performing thePWL approximations comprises performing a first processing cycle,including: performing a multiplication operation to multiply an inputdata value and a first interval version of a first parameter value;performing a subtraction operation of a first interval version of asecond parameter from the result of the multiplication operation; andsetting an enable bit indicating a sign of the result of the subtractionoperation.
 11. The method of claim 10, further comprising performing asecond processing cycle, including: performing an addition operation ofa first interval version of a third parameter and the result of thesubtraction operation during a second processing cycle of the PWLapproximation.
 12. The method of claim 11, further comprisingdetermining whether the enable bit indicates that the sign of the resultof the subtraction operation has a first value.
 13. The method of claim12, further comprising performing a third processing cycle, including:performing a second multiplication operation of the input data value anda second interval version of the first parameter value upon adetermination that the enable bit indicates that the has the firstvalue; and performing a second subtraction operation of a secondinterval version of the second parameter from the result of the secondmultiplication operation.
 14. The method of claim 12, further comprisingsaving a result of the addition operation upon a determination that thesign has a second value.
 15. An accelerator comprising: one or morememory devices to store one or more one or more lookup tables (LUTs);and a compute grid having a plurality of a plurality of tiles, eachincluding a plurality of processing elements to execute neural networkcomputations, store values resulting from the neural networkcomputations, and perform piecewise linear (PWL) approximations of oneor more non-linear functions using the stored values as input data andnon-linear parameter values stored in the one or more LUTs.
 16. Theaccelerator of claim 15, wherein each of the plurality of processingelements comprises: a first stage including a multiplier to perform amultiplication operation of an input data value and a first intervalversion of a first parameter value during a first processing cycle of aPWL approximation; and a second stage including an accumulator toperform a subtraction operation of a first interval version of a secondparameter from a result of the multiplication operation.
 17. Theaccelerator of claim 16, wherein the accumulator sets an enable bitindicating a sign of the result of the subtraction operation.
 18. Theaccelerator of claim 17, wherein the accumulator performs an additionoperation of a first interval version of a third parameter and theresult of the subtraction operation during a second processing cycle ofthe PWL approximation.
 19. The accelerator of claim 18, wherein adetermination is made as to whether the enable bit indicates that thesign of the result of the subtraction operation has a first value. 20.The accelerator of claim 19, wherein the multiplier performs a secondmultiplication operation of the input data value and a second intervalversion of the first parameter value during a third processing cycle ofa PWL approximation upon a determination that the enable bit indicatesthat the has the first value, and the accumulator performs a secondsubtraction operation of a second interval version of the secondparameter from a result of the second multiplication operation.
 21. Theaccelerator of claim 19, wherein a result of the addition operation issaved as the PWL approximation upon a determination that the sign has asecond value.